1. Field of the Invention
The present invention relates to a semiconductor memory device having a plurality of memory blocks which achieves a high-speed operation by reducing a pre-charge time during an active operation of a word line. More particularly, it relates to a semiconductor memory device which pre-charges other blocks simultaneously while activating a previously activated block, thereby preventing the waste of a pre-charge time.
2. Description of the Prior Art
Generally, a semiconductor memory device is a logic element having a square-type matrix structure storing an electric digital signal therein, and has an address for designating each storage position. These addresses are called a row address and a column address, respectively.
The memory cells having a two-dimensional matrix structure of the square-type include a word line and a bit line on which data of a designated word line is output. Herein, an address of designating the word line is called a row address, and an address of designating the bit line is called a column address.
Hereinafter, a method for inputting/outputting data to a corresponding address in a DRAM will be described.
First, if a signal /RAS (i.e., /row address strobe) is activated as a low value and a row address is applied at the same time, one word line in a two-dimensional square-type memory structure is activated, thereby activating a plurality of cells connected to the word line. Minute electric signals of the cells connected to the word line once activated are amplified by an operation of a sense-amp and are then outputted.
After that, if the operation of the sense-amp is completed, one cell is selected by an operation of a column address signal applied in response to an activation of a signal /CAS (i.e., /column address strobe), and data of the selected cell is outputted to the outside.
However, the memory cells have a block structure in which a plurality of cells involved in the same block by an address designation is under the control of the same sense-amp and is simultaneously operated regardless of a data input/output operation. An address for designating a blocked unit block is called a block address, and this block address is selected among row addresses.
Accordingly, in case that one word line among the memory cells having the above block structure is activated, one column is designated, and a data output operation is achieved, the selected row address becomes pre-charged and returns to an inactive state. At this time, the time required from a command designating a precharge state to a completion of the precharge state is called a time tRP in a product specification.
However, since the conventional art arranges a most significant bit (MSB) in designating the block address, the block address is hardly changed during memory connection time. To reactivate other word lines involved in the same block after activating one word line, the time tRP should be elapsed. That is, since the conventional art has the following operation method, (i.e., a successive word line activation .fwdarw. read or write operation .fwdarw. a wait state during a pre-charge time .fwdarw. the next word line activation .fwdarw. read or write operation .fwdarw. a wait state during a pre-charge time, . . . ), unnecessary wait time is needed at intervals during a memory connection, thereby preventing a high-speed operation.
FIG. 1 is a timing diagram illustrating an operation of the conventional dynamic random access memory (DRAM). FIG. 1 shows that the time for pre-charging a previous word line is required before other word lines are activated, after performing a read operation by an activation of one word line involved in the same block. Accordingly, the time tRP required from a command designating a pre-charge state to a completion of the pre-charge state is positively needed in the conventional DRAM.
In case of a synchronous DRAM having a bank structure, if other banks are alternately activated and a ping-pong operation is performed, the aforementioned problem regarding the waste of the time tRP is capable of being solved. But, in case of a chip-set not supporting such a ping-pong operation of the bank structure or a general DRAM (i.e., standard DRAM), a high-speed operation of an entire system is prevented due to the time tRP.